[PEDA] Thermal Impedance of Copper Areas

[ajenkins@avtron.com]

A dense grid of vias can be used as heat pipes to land(s) the other side
of the board. I think I read a usage note from Burr Brown for one of its
5DDPAK pkg amplifiers (or perhaps it was another mfgs app note) a few
years ago that described the use of vias for increasing the effective
area (heat is absorbed by a copper land proprotional to the thermal
difference between the trasmitting (IC) and receiving (connected copper
land) substrates. As was said in another post, a secondary heat sink can
be mounted on the other side of the board, either for direct conductive
release to an enclosure or similar, or to an active device such as a
peltier cooler and/or fan/heatsink... For more detailed information
regarding thermal transfer, one might consult a second or third year
Thermodynamics text book. Unfortunately, my present job doesn't afford
me anything more than time to write what is above.

I've used grids with 10-15 mil vias and spacings as small as 50 mils,
but the area is of course usable only for heat sinking. 

aj

>-----Original Message-----
>From: PEDA-bounces at techservinc.com 
>[mailto:PEDA-bounces at techservinc.com] On Behalf Of Linden
>Sent: Wednesday, July 26, 2006 8:25 PM
>To: PEDA at techservinc.com
>Subject: [PEDA] Thermal Impedance of Copper Areas
>
>Greetings All,
>
>Can anyone direct me to information on the relationship 
>between copper area and thermal impedance for SMD devices?
>
>I have a D2PAK MOSFET that has a Thermal impedance of 40K/W 
>junction to ambient when mounted with a minimum of copper on 
>the mounting tab..
>I'd like to reduce this figure by adding a copper area 
>(polygon or fill) to the mounting tab.
>The problem is I don't have a feel for how much copper is 
>needed for a particular reduction in thermal impedance.
>
>
>Thanks in advance,
>
>Linden Doyle
>
>
>
>
>
> 
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